A standardized way to provide test access to digital pin signals of an IC is to implement digital boundary scan according to the rules defined in the “IEEE Standard Test Access Port and Boundary-Scan Architecture”, published by the Institute for Electrical and Electronic Engineers (IEEE), which is also known as IEEE Std 1149.1-2001, or simply 1149.1. A dominant characteristic of 1149.1 is the use of a Test Access Port (TAP) controller and a shift register referred to as the Boundary Scan Register (BSR).
The cost of automatic test equipment that tests ICs is proportional to the number of IC pins to be accessed, and the required measurement accuracy. Circuitry on an IC that is consistent with 1149.1 can facilitate reduced pin-count (RPC) access to the IC, which significantly reduces the cost of the tester needed to test the IC. To facilitate RPC test access, pin circuitry is made bi-directional and boundary scan circuitry is added as shown in FIG. 1. An output driver 11 may be enabled by an Enable bit in the boundary scan cell (BSC) 2, and the output Data value and/or captured Data value is stored in BSC 1.
In “A Cost/Benefit Analysis of the P1149.4 Mixed Signal Test Bus,” by Sunter in IEE Proceedings, Circuits, Devices, and Systems, December 1996, it is noted that the IEEE “P1149.4 bus allows testing of [pin] parameters without requiring a probe for each pad.” The circuit described uses an analog bus to access the voltage or logic value at each pin. An all-digital circuit is desired to provide a faster, more robust measurement.
In U.S. Pat. No. 5,621,739 by Sine et al. in 1997, an IC's input/output (I/O) buffer is self-tested by utilizing “an adjustable delay circuit to test whether the buffer can capture a data value during a variable strobe window.” It includes a comparison circuit to detect whether the captured data value matches an expected value. In U.S. Pat. No. 6,058,496 by Gillis et al. in 2000, and “Delay test of Chip I/Os Using LSSD Boundary Scan” by Gillis et al. in Proceedings of the 1996 International Test Conference, an adjustably-timed series of clock edges clocks boundary scan latches to launch data edges to a pin of the IC and another boundary scan latch captures the pin's logic value, to enable measuring delays between a path including the pin and a path not including the pin, without tester or load connections to the pin “that can degrade accuracy of testing.” One embodiment adjusts the clock edge times in the tester, and another embodiment adjusts an on-chip delay line. The launch and capture times are controlled by separate clocks having the same frequency but an adjustable phase offset. Delay circuits on an IC (“on-chip”) have significant jitter caused by power supply noise and significant delay variation caused by temperature and processing variations. Delay resolution achievable with purely digital delay circuits is usually equal to the delay of a logic gate. A circuit that avoids the use of on-chip adjustable delays and tester-adjusted phase offsets would advantageously permit accurate self-testing an IC in a system that includes connections to components external to the IC (“off-chip”). Furthermore, the measurement's relevance can be improved if external load impedances comparable to that in the IC's intended application are connected while measuring I/O performance.
In U.S. Pat. No. 6,586,921 by Sunter et al. in 2003, incorporated herein by reference, the leakage current at an IC's I/O pin is tested, without tester connections to the pin, using the circuit of FIG. 1 and the signal timing shown in FIG. 2. In that method, the pin is driven to a data value and at a time t1 the pin is tri-stated. At a pre-determined later time t2, the pin's logic value is captured. If the logic value is the same as the originally driven data value, then the leakage current is lower than a pre-determined threshold current. If an off-chip capacitance is connected to the pin, then the time t2 is chosen to be later by an amount proportional to the increase in total pin capacitance. If an off-chip pull-up or pull-down resistance is connected to the pin, then the pin's current will include current flowing through the resistance, and the time t2 is chosen to be sooner by an amount proportional to the increase in total current flowing through the pin (equal to leakage current plus current through the resistance). A circuit that can generate edges with fine resolution in a range of capture times between t1 and t2 would advantageously permit in-system testing of higher leakage currents and lower resistances.
In U.S. Pat. No. 6,724,210 by Combs et al. in 2004, the presence of a chip-to-package connection is determined by detecting an increase in the delay of the pin driver relative to its unloaded delay, and, since the delay increase is normally imperceptible, substitutes an especially weak driver so that the delay increase is more easily detected. It is also noted that the delay could be compared “with one or more characteristics of another I/O” so that sensitivity to normal variations between ICs is reduced. A circuit that does not require any modification to normal output drivers and boundary scan circuitry would advantageously avoid re-designing existing circuitry and minimize impact on driver performance. A circuit that compared a measured delay to the average characteristic value of multiple I/Os would further reduce the test's sensitivity to normal variations in ICs.
In U.S. Pat. No. 7,453,255 by Sunter et al. in 2008, incorporated herein by reference, circuitry is described that can “measure the delays of input and output circuitry that is controlled by a boundary scan resister within an IC.” The circuit uses an undersampling clock whose frequency is slightly different from the undersampled signal's clock frequency divided by an integer, and measures the delay between median edge positions of the undersampled signal by producing “a combined output whose duty cycle is proportional to the time interval.” The circuit measures one set of boundary scan cell delays relative to a common clock, and then a second set of delays that include the I/O pad drivers, and then subtracts each delay of the first set from the corresponding delay of the second set. A measurement circuit is desired that can be simple enough to incorporate on-chip economically for in-system measurements of many I/O circuits simultaneously, and that can measure a delay difference between two circuit paths, or between two conditions of one circuit path, without measuring each delay separately since each delay involves two edges and hence four sources of variation per delay difference, and without combining two undersampled signals to produce a duty cycle since only one signal is accessible at a time via a boundary scan shift register.
In “A General Strategy for BIST of High-Speed Analog Functions”, by Sunter in the informal proceedings of the Workshop on Test and Verification of High-Speed Analog Circuits, November 2009, it is shown how the technique described above herein in the Sunter patent '255 and in U.S. Pat. No. 7,158,899 by Sunter et al., incorporated herein by reference, can be applied to measuring analog circuit parameters by converting the parameters to periodic time delays whose duty cycle or jitter can be measured. According to that paper, one measurement circuit can measure one parameter for one circuit at a time. It is desired to measure timing properties derived from parameters for many analog circuits simultaneously (i.e., in parallel) to reduce total measurement time.
Note that bond pads of a bare IC die may be connected to the pins of an encapsulating package, or to another component within such a package. In this disclosure, “pin”, “bond pad” and “pad” will be used interchangeably. A pad may be considered to be merely an enlarged metal area of a wire path that has a driver and a receiver. An “I/O” will be considered as any node of a circuit under test (CUT) at which signals may be injected or monitored, especially nodes that are primary inputs or outputs of ICs. An I/O may be a pin or pad, or a through-silicon via (TSV), or simply an on-chip connection to another on-chip logic gate.
It is desirable to accurately and automatically measure delays of paths within an IC, especially paths that include I/O pin driver and receiver delays, with or without off-chip connections, without using adjustable delay lines or off-chip measuring equipment, and without precisely-timed clock edges from outside the IC, other than clocks with known frequencies. “Measure” means generate a (binary-coded) number that is proportional to a delay of interest. Delays of interest include, but are not limited to, data and control signal propagation delays for rising and falling transitions. The delay may be dominated by inherent propagation of a signal through a driver and receiver, the capacitance of the driver's load, the inherent leakage current of a tri-stated driver output, the resistance of a pull-up or pull-down resistor, and any of various other comparable delays. Delay measuring usually includes irrelevant delays, for example the delay from a measurement circuit to a path of interest, so it is an objective of the present invention to measure delay differences or changes, so that irrelevant delays can be cancelled (subtracted) from the measurement result. It is also desirable to test delays, where “test” means to measure and then compare the measurement to upper and/or lower limits to produce a pass/fail result.
It is further desirable to test many such delays simultaneously since an IC may have hundreds or thousands of path delays to be measured, including I/O paths. It is still further desirable to test mismatches between signal rise and fall delays for a path, and between delays for multiple I/Os, and between delays within a group and the average delay of the group. It is still further desirable to test delay-related parameters of multiple analog circuits simultaneously because analog circuits often have long time constants (settling delays) so measuring their parameters in parallel is an effective way to reduce total measurement time.